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? semiconductor components industries, llc, 2001 june, 2001 rev. 3 1 publication order number: mc74lvxc3245/d mc74lvxc3245 configurable dual supply octal transceiver with 3state outputs for 3 v systems the 74lvxc3245 is a 24pin dualsupply, octal configurable voltage interface transceiver especially well suited for pcmcia and other real time configurable i/o applications. the v cca pin accepts a 3 v supply level; the a port is a dedicated 3 v port. the v ccb pin accepts a 3 vto5 v supply level. the b port is configured to track the v ccb supply level. a 5 v level on the v ccb pin will configure the i/o pins at a 5 v level and a 3 v v ccb will configure the i/o pins at a 3 v level. the a port interfaces with a 3 v host system and the b port to the card slots. this device will allow the v ccb voltage source pin and i/o pins on the b port to float when oe is high. this feature is necessary to buffer data to and from a pcmcia socket that permits pcmcia cards to be inserted and removed during normal operation. the transmit/receive (t/r ) input determines the direction of data flow. transmit (activehigh) enables data from the a port to b port. receive (activelow) enables data from the b port to the a port. ? bidirectional interface between 3 v and 3 v/5 v buses ? control inputs compatible with ttl level ? outputs source/sink up to 24 ma ? guaranteed simultaneous switching noise level and dynamic threshold performance ? available in soic and tssop packages ? flexible v ccb operating range ? allows b port and v ccb to float simultaneously when oe is high ? functionally compatible with the 74 series 245 http://onsemi.com so24 dw suffix case 751e tssop24 dt suffix case 948h marking diagrams 1 24 lvxc3245 awlyyww a = assembly location wl = wafer lot yy = year ww = work week device package shipping ordering information mc74lvxc3245dt so24 62 units/rail so24 tssop24 2500 tape/reel 30 units/rail tssop24 1000 tape/reel mc74lvxc3245dtr2 mc74lvxc3245dw mc74lvx540dtr2 lvx 3245 awlyyww 1 24 1 24 1 24
mc74lvxc3245 http://onsemi.com 2 b0 oe 22 t/r 2 a0 b1 a1 b2 a2 b3 a3 b4 a4 b5 a5 b6 a6 b7 a7 3 4 5 6 7 8 9 10 21 20 19 18 17 16 15 14 figure 1. 24lead pinout (top view) 23 24 22 21 20 19 18 2 1 34567 v ccb 17 8 16 9 15 10 nc oe b0 b1 b2 b3 b4 b5 b6 v cca t/r a0 a1 a2 a3 a4 a5 a6 a7 14 11 13 12 b7 gnd gnd gnd figure 2. logic diagram pin names function output enable input transmit/receive input side a 3state inputs or 3state outputs side b 3state inputs or 3state outputs pins oe t/r a0a7 b0b7 inputs operating mode oe t/r o peratin g m o de noninverting l l b data to a bus l h a data to b bus h x z h = high voltage level; l = low v oltage level; z = high impedance state; x = high or low voltage level and transitions are acceptable; for i cc reasons, do not float inputs
mc74lvxc3245 http://onsemi.com 3 maximum ratings symbol parameter value condition unit v cca , v ccb dc supply voltage 0.5 to +7.0 v v i dc input voltage oe , t/r 0.5 to v cca +0.5 v v i/o dc input/output voltage an 0.5 to v cca +0.5 v bn 0.5 to v ccb +0.5 v i ik dc input diode current oe , t/r 20 v i < gnd ma i ok dc output diode current 50 v o < gnd; v o > v cc ma i o dc output source/sink current 50 ma i cc , i gnd dc supply current per output pin maximum current 50 200 ma t stg storage temperature range 65 to +150 c dc latchup source/sink current 300 ma maximum ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute maximumrated conditions is not implied. functional operation should be restricted to the recommended operating conditions. recommended operating conditions symbol parameter min max unit v cca , v ccb supply voltage (v cca v ccb )v cca v ccb 2.3 3.0 3.6 5.5 v v i input voltage oe , t/r 0 v cca v v i/o input/output voltage an bn 0 0 v cca v ccb v t a operating freeair temperature 40 +85 c d t/ d v minimum input edge rate v in from 30% to 70% of v cc ; v cc at 3.0 v, 4.5 v, 5.5 v 0 8 ns/v dc electrical characteristics t a = 25 c t a = 40 to +85 c symbol parameter condition v cca v ccb typ guaranteed limits unit v iha minimum high level input voltage an oe t/r v out 0.1 v or 2.3 3.0 3.6 3.0 3.6 5.5 2.0 2.0 2.0 2.0 2.0 2.0 v v ihb bn or v cc 0.1 v 2.3 3.0 3.6 3.0 3.6 5.5 2.00 2.00 3.85 2.00 2.00 3.85 v v ila maximum low level input voltage an oe t/r v out 0.1 v or 2.3 3.0 3.6 3.0 3.6 5.5 0.8 0.8 0.8 0.8 0.8 0.8 v v ilb bn or v cc 0.1 v 2.3 3.0 3.6 3.0 3.6 5.5 0.80 0.80 1.65 0.80 0.80 1.65 v v oha minimum high level output voltage i out = 100 m a i oh = 12 ma i oh = 24 ma i oh = 12 ma i oh = 24 ma 3.0 3.0 3.0 2.3 2.3 3.0 3.0 3.0 3.0 4.5 2.99 2.85 2.65 2.50 2.30 2.90 2.56 2.35 2.30 2.10 2.90 2.46 2.25 2.20 2.00 v v ohb i out = 100 m a i oh = 12 ma i oh = 24 ma i oh = 24 ma 3.0 3.0 3.0 3.0 3.0 3.0 3.0 4.5 2.99 2.85 2.65 4.25 2.90 2.56 2.35 3.86 2.90 2.46 2.25 3.76 v
mc74lvxc3245 http://onsemi.com 4 dc electrical characteristics t a = 40 to +85 c t a = 25 c symbol unit guaranteed limits typ v ccb v cca condition parameter v ola maximum low level output voltage i out = 100 m a i ol = 24 ma i ol = 12 ma i ol = 24 ma 3.0 3.0 2.7 2.7 3.0 3.0 3.0 4.5 0.002 0.21 0.11 0.22 0.10 0.36 0.36 0.42 0.10 0.44 0.44 0.50 v v olb i out = 100 m a i ol = 24 ma i ol = 24 ma 3.0 3.0 3.0 3.0 3.0 4.5 0.002 0.21 0.18 0.10 0.36 0.36 0.10 0.44 0.44 v i in max input leakage current oe , t/r v i = v cca , gnd 3.6 3.6 3.6 5.5 0.1 0.1 1.0 1.0 m a i oza max 3state output leakage an v i = v ih , v il oe = v cca v o = v cca , gnd 3.6 3.6 3.6 5.5 0.5 0.5 5.0 5.0 m a i ozb max 3state output leakage bn v i = v ih , v il oe = v cca v o = v ccb , gnd 3.6 3.6 3.6 5.5 0.5 0.5 5.0 5.0 m a d i cc maximum i cc /input bn v i = v ccb 2.1 v 3.6 5.5 1.0 1.35 1.5 ma all inputs v i = v cc 0.6 v 3.6 3.6 0.35 0.5 ma i cca1 quiescent v cca supply current as b port floats an = v cca or gnd bn = open, oe = v cca , t/r = v cca , v ccb = open 3.6 open 5 50 m a i cca2 quiescent v cca supply current an = v cca or gnd bn = v ccb or gnd, oe = gnd, t/r = gnd 3.6 3.6 3.6 5.5 5 5 50 50 m a i ccb quiescent v ccb supply current an = v cca or gnd bn = v ccb or gnd, oe = gnd, t/r = v cca 3.6 3.6 3.6 5.5 5 8 50 80 m a v olpa quiet output max dynamic v ol notes 1., 2. 3.3 3.3 3.3 5.0 0.8 0.8 v v olpb notes 1., 2. 3.3 3.3 3.3 5.0 0.8 1.5 v v olva quiet output min dynamic v ol notes 1., 2. 3.3 3.3 3.3 5.0 0.8 0.8 v v olvb notes 1., 2. 3.3 3.3 3.3 5.0 0.8 1.2 v v ihda min high level dynamic input volt- age notes 1., 3. 3.3 3.3 3.3 5.0 2.0 2.0 v v ihdb notes 1., 3. 3.3 3.3 3.3 5.0 2.0 3.5 v v ilda max low level dynamic input volt- age notes 1., 3. 3.3 3.3 3.3 5.0 0.8 0.8 v v ildb notes 1., 3. 3.3 3.3 3.3 5.0 0.8 1.5 v 1. worst case package. 2. max number of outputs defined as (n). data inputs are driven 0 v to v cc level; one output at gnd. 3. max number of data inputs (n) switching. (n1) inputs switching 0 v to v cc level. input under test switching: v cc level to threshold (v ihd ), 0 v to threshold (v ild ), f = 1 mhz.
mc74lvxc3245 http://onsemi.com 5 ac electrical characteristics t a = 40 to +85 c; c l = 50 pf v cca = 2.73.6 v v ccb = 4.55.5 v v cca = 2.73.6 v v ccb = 3.03.6 v symbol parameter min typ (note 4.) max min typ (note 5.) max unit t phl t plh propagation delay a to b 1.0 1.0 4.8 3.9 8.5 7.0 1.0 1.0 5.5 5.2 9.0 8.5 ns t phl t plh propagation delay b to a 1.0 1.0 3.8 4.3 7.0 8.0 1.0 1.0 4.4 5.1 7.5 8.0 ns t pzl t pzh output enable time oe to b 1.0 1.0 4.7 4.8 8.5 9.0 1.0 1.0 6.0 6.1 9.5 10.0 ns t pzl t pzh output enable time oe to a 1.0 1.0 5.9 5.4 10.0 9.5 1.0 1.0 6.4 5.8 10.5 9.5 ns t phz t plz output disable time oe to b 1.0 1.0 4.0 3.8 8.5 8.0 1.0 1.0 6.3 4.5 10.0 8.5 ns t phz t plz output disable time oe to a 1.0 1.0 4.6 3.1 10.0 7.0 1.0 1.0 5.2 3.4 10.0 7.0 ns t oshl t oslh output to output skew, data to output (note 6.) 1.0 1.5 1.0 1.5 ns 4. typical values at v cca = 3.3 v, v ccb = 5.0 v at 25 c. 5. typical values at v cca = 3.3 v, v ccb = 3.3 v at 25 c. 6. skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same d evice. the specification applies to any outputs switching in the same direction, either hightolow (t oshl ) or lowtohigh (t oslh ); parameter guaranteed by design. capacitive characteristics symbol parameter condition typical unit c in input capacitance v cca = 3.3 v; v ccb = 5.0 v 4.5 pf c i/o input/output capacitance v cca = 3.3 v; v ccb = 5.0 v 10 pf c pd power dissipation capacitance a b (measured at 10 mhz) b a v ccb = 5.0 v v cca = 3.3 v 50 40 pf
mc74lvxc3245 http://onsemi.com 6 figure 3. block diagram slot 0 lvxc3245 lvxc3245 slot 1 lvxc3245 lvxc3245 slot 0 slot 1 v ccb v cca optional 5 v v cc 3 v v cc power switches pcmcia 2.0 jeida 4.1 compatible controller sd(0:15) sd(0:15) isa bus (ieee p996) configurable i/o application for pcmcia cards the 74lvxc3245 is a dualsupply device well suited for pcmcia configurable i/o applications. the lvxc3245 consumes less than 1mw of quiescent power in all modes of operation, making it ideal for low power notebook designs. the lvxc3245 meets all pcmcia i/o voltage requirements at 5 v and 3.3 v operation. by tying the v ccb pin to the card voltage supply, the pcmcia card will always have railtorail output swings, maximizing the reliability of the interface. the v cca pin must always be tied to a 3.3 v power supply. this voltage connection provides internal references needed to account for variations in v ccb . when connected as in the figure above, the lvxc3245 meets all the voltage and current requirements of the isa bus standard (ieee p996).
mc74lvxc3245 http://onsemi.com 7 waveform 1 - propagation delays t r = t f = 2.5 ns, 10% to 90%; f = 1 mhz; t w = 500 ns v cc 0 v v oh v ol an, bn bn, an t phl t plh waveform 2 - output enable and disable times t r = t f = 2.5 ns, 10% to 90%; f = 1 mhz; t w = 500 ns v cc 0 v 0 v oe , t/r an, bn t pzh v cc t phz t pzl t plz an, bn 50% v cc 50% v cc 50% v cc 50% v cc 50% v cc 50% v cc figure 4. ac waveforms 50% v cc v cc v oh - 0.3 v v ol + 0.3 v gnd 50% v cc open pulse generator r t dut v cc r l r 1 c l 2xv cc test switch t plh , t phl , t pzh , t phz open t pzl , t plz 2xv cc c l = 50 pf or equivalent (includes jig and probe capacitance) r l = r 1 = 500 w or equivalent r t = z out of pulse generator (typically 50 w ) figure 5. test circuit
mc74lvxc3245 http://onsemi.com 8 outline dimensions dw suffix so24 package case 751e04 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b p 12x d 24x 12 13 24 1 m 0.010 (0.25) b m s a m 0.010 (0.25) b s t t g 22x seating plane k c r x 45 m f j dim min max min max inches millimeters a 15.25 15.54 0.601 0.612 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.41 0.90 0.016 0.035 g 1.27 bsc 0.050 bsc j 0.23 0.32 0.009 0.013 k 0.13 0.29 0.005 0.011 m 0 8 0 8 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029
mc74lvxc3245 http://onsemi.com 9 outline dimensions dt suffix plastic tssop package case 948h01 issue o dim min max min max inches millimeters a 7.70 7.90 0.303 0.311 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l u seating plane 0.10 (0.004) t ??? ??? ??? section nn detail e j j1 k k1 detail e f m w 0.25 (0.010) 13 24 12 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t v 24x ref k n n
mc74lvxc3245 http://onsemi.com 10 notes
mc74lvxc3245 http://onsemi.com 11 notes
mc74lvxc3245 http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc74lvxc3245/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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